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» On the Complexity of Circuit Satisfiability
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DAC
2004
ACM
14 years 10 months ago
An approach to placement-coupled logic replication
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
Milos Hrkic, John Lillis, Giancarlo Beraudo
DAC
2005
ACM
14 years 10 months ago
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubn...
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 9 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
STOC
2010
ACM
216views Algorithms» more  STOC 2010»
14 years 6 months ago
BQP and the Polynomial Hierarchy
The relationship between BQP and PH has been an open problem since the earliest days of quantum computing. We present evidence that quantum computers can solve problems outside th...
Scott Aaronson
ICCAD
2007
IEEE
131views Hardware» more  ICCAD 2007»
14 years 6 months ago
Low-overhead design technique for calibration of maximum frequency at multiple operating points
— Determination of maximum operating frequencies (Fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a Dynamic Voltage and Fr...
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid...