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» On the Complexity of Circuit Satisfiability
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DATE
2007
IEEE
130views Hardware» more  DATE 2007»
14 years 3 months ago
A novel criticality computation method in statistical timing analysis
Abstract— The impact of process variations increases as technology scales to nanometer region. Under large process variations, the path and arc/node criticality [18] provide effe...
Feng Wang 0004, Yuan Xie, Hai Ju
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
14 years 3 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
ISLPED
2006
ACM
122views Hardware» more  ISLPED 2006»
14 years 3 months ago
Dynamic thermal clock skew compensation using tunable delay buffers
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
ISPD
2006
ACM
84views Hardware» more  ISPD 2006»
14 years 3 months ago
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
Mongkol Ekpanyapong, Sung Kyu Lim