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» On the Complexity of Circuit Satisfiability
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ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
14 years 5 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim
ISCAS
2006
IEEE
144views Hardware» more  ISCAS 2006»
14 years 2 months ago
A VLSI spike-driven dynamic synapse which learns only when necessary
— We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is hi...
S. Mitra, Stefano Fusi, Giacomo Indiveri
ASPDAC
2006
ACM
130views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen...
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 2 months ago
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, whic...
Zhong Wang, Jianwen Zhu
ISCAS
2003
IEEE
153views Hardware» more  ISCAS 2003»
14 years 2 months ago
A VLSI model of range-tuned neurons in the bat echolocation system
The neural computations that support bat echolocation are of great interest to both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the ...
Matthew Cheely, Timothy K. Horiuchi