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» On the Complexity of Loop Fusion
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ISSS
1998
IEEE
104views Hardware» more  ISSS 1998»
14 years 1 months ago
Synchronization Detection for Multi-Process Hierarchical Synthesis
Complex system specifications are often hierarchically composed of several subsystems. Each subsystem contains one or more processes. In order to provide optimization across diffe...
Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reicha...
CAV
1998
Springer
108views Hardware» more  CAV 1998»
14 years 1 months ago
Decomposing the Proof of Correctness of pipelined Microprocessors
We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction funct...
Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalak...
ICCAD
1994
IEEE
74views Hardware» more  ICCAD 1994»
14 years 29 days ago
Non-scan design-for-testability of RT-level data paths
- This paper presents a non-scan design-for-testability technique applicable to register-transfer(RT) level data path circuits, which are usually very hard-to-test due to the prese...
Sujit Dey, Miodrag Potkonjak
CCGRID
2004
IEEE
14 years 18 days ago
An interactive Grid for non-invasive vascular reconstruction
We conduct computer simulation experiments in pre-operative planning of vascular reconstruction with a physician in the experimental loop. We constructed a problem-solving environ...
Peter M. A. Sloot, Alfredo Tirado-Ramos, Alfons G....
ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
14 years 13 days ago
New efficient algorithms for computing effective capacitance
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
Andrew B. Kahng, Sudhakar Muddu