New efficient algorithms for computing effective capacitance

We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than previous methods for computing effective capacitance, with little or no loss of accuracy. Thus, the approach is suitable within the analysis loop for performance-driven iterative layout optimization. After reviewing previous gate load models and effective capacitance approximations, we separately derive our method for the cases of step and ramp waveform at the gate output, and note ongoing extensions for the case of complex gates (e.g., channel-connected components). Experimental results using the new effective capacitance approach show that our resulting delay estimates are quite accurate

• Type: Conference
• Year: 1998
• Where: ISPD
• Authors: Andrew B. Kahng, Sudhakar Muddu
• Keywords: Effective Capacitance, Effective Capacitance Approach, Gate Output, Hardware, ISPD 1998