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» On the Complexity of Register Coalescing
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DAC
2000
ACM
14 years 8 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
14 years 24 days ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson
TCAD
2010
90views more  TCAD 2010»
13 years 2 months ago
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration
The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
CVPR
2009
IEEE
15 years 2 months ago
Image Registration by Minimization of Residual Complexity
Accurate denition of similarity measure is a key component in image registration. Most commonly used intensitybased similarity measures rely on the assumptions of independence ...
Andriy Myronenko, Xubo B. Song
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
14 years 24 days ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...