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» On the Complexity of Register Coalescing
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FMCAD
2009
Springer
14 years 2 months ago
Retiming and resynthesis with sweep are complete for sequential transformation
— There is a long history of investigations and debates on whether a sequence of retiming and resynthesis is complete for all sequential transformations (on steady states). It ha...
Hai Zhou
ISCA
2005
IEEE
131views Hardware» more  ISCA 2005»
14 years 1 months ago
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging
Significant time is spent by companies trying to reproduce and fix the bugs that occur for released code. To assist developers, we propose the BugNet architecture to continuousl...
Satish Narayanasamy, Gilles Pokam, Brad Calder
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
14 years 1 months ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich
MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
13 years 11 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
MICRO
1993
IEEE
127views Hardware» more  MICRO 1993»
13 years 11 months ago
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
Ing-Jer Huang, Alvin M. Despain