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» On the Complexity of Register Coalescing
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TCAD
2011
13 years 2 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...
ECCV
2008
Springer
14 years 9 months ago
Higher Dimensional Affine Registration and Vision Applications
Abstract. Affine registration has a long and venerable history in computer vision literature, and extensive work have been done for affine registrations in IR2 and IR3 . In this pa...
Yu-Tseh Chi, S. M. Nejhum Shahed, Jeffrey Ho, Ming...
STOC
2004
ACM
158views Algorithms» more  STOC 2004»
14 years 7 months ago
Collective asynchronous reading with polylogarithmic worst-case overhead
The Collect problem for an asynchronous shared-memory system has the objective for the processors to learn all values of a collection of shared registers, while minimizing the tot...
Bogdan S. Chlebus, Dariusz R. Kowalski, Alexander ...
IPPS
2009
IEEE
14 years 2 months ago
High-order stencil computations on multicore clusters
Stencil computation (SC) is of critical importance for broad scientific and engineering applications. However, it is a challenge to optimize complex, highorder SC on emerging clus...
Liu Peng, Richard Seymour, Ken-ichi Nomura, Rajiv ...
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 1 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...