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DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 18 days ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
ISCAS
2005
IEEE
141views Hardware» more  ISCAS 2005»
14 years 1 months ago
Fast-scale instability of single-stage power-factor-correction power supplies
Abstract— This paper describes the fast-scale bifurcation phenomena of a single-stage power-factor-correction (PFC) power supply which is commonly used in low power applications....
Xiaoqun Wu, Chi Kong Tse, Octavian Dranga, Junan L...
DAC
2005
ACM
13 years 9 months ago
A combined feasibility and performance macromodel for analog circuits
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a num...
Mengmeng Ding, Ranga Vemuri
DAC
2004
ACM
13 years 11 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
DAC
2005
ACM
14 years 8 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo