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» On the Design of IEEE Compliant Floating Point Units
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ARITH
2007
IEEE
14 years 2 months ago
Optimistic Parallelization of Floating-Point Accumulation
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...
Nachiket Kapre, André DeHon
DATE
2009
IEEE
109views Hardware» more  DATE 2009»
14 years 2 months ago
Improving yield and reliability of chip multiprocessors
— An increasing number of hardware failures can be attributed to device reliability problems that cause partial system failure or shutdown. In this paper we propose a scheme for ...
Abhisek Pan, Omer Khan, Sandip Kundu
ARITH
2011
IEEE
12 years 7 months ago
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
Neil Burgess
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 1 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
PACS
2000
Springer
118views Hardware» more  PACS 2000»
13 years 11 months ago
Ramp Up/Down Functional Unit to Reduce Step Power
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....