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» On the Fault Testing for Reversible Circuits
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ET
2002
84views more  ET 2002»
13 years 7 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
GLVLSI
2003
IEEE
161views VLSI» more  GLVLSI 2003»
14 years 25 days ago
TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits
The characterization as well as the control of the electromagnetic emission of integrated circuits is an important step in the design process of state of the art integrated circui...
Timm Ostermann, Bernd Deutschmann
ISMVL
2007
IEEE
92views Hardware» more  ISMVL 2007»
14 years 1 months ago
Experimental Studies on SAT-Based ATPG for Gate Delay Faults
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
Stephan Eggersglüß, Daniel Tille, G&oum...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
14 years 26 days ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
VTS
2000
IEEE
94views Hardware» more  VTS 2000»
13 years 12 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng