Sciweavers

372 search results - page 49 / 75
» On the Fault Testing for Reversible Circuits
Sort
View
ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
14 years 4 months ago
Temperature-aware test scheduling for multiprocessor systems-on-chip
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...
David R. Bild, Sanchit Misra, Thidapat Chantem, Pr...
ATS
1998
IEEE
112views Hardware» more  ATS 1998»
13 years 11 months ago
Integrated Current Sensing Device for Micro IDDQ Test
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
Koichi Nose, Takayasu Sakurai
VLSID
2005
IEEE
120views VLSI» more  VLSID 2005»
14 years 1 months ago
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattachar...
DFT
1997
IEEE
93views VLSI» more  DFT 1997»
13 years 11 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
14 years 1 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal