372 search results - page 51 / 75 » On the Fault Testing for Reversible Circuits |
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
EVOW
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. We motivate and describe an analog evolvable hardware design platform named GRACE (i.e. Generative Robust Analog Circuit Exploration). GRACE combines coarse-grained, topo...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
TVLSI
2008
13 years 7 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...