372 search results - page 54 / 75 » On the Fault Testing for Reversible Circuits |
VLSID
1998
IEEE
13 years 11 months ago
1998
IEEE
A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-d...
EAAI
2007
13 years 7 months ago
2007
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...