372 search results - page 73 / 75 » On the Fault Testing for Reversible Circuits |
CASES
2009
ACM
14 years 4 days ago
2009
ACM
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this...
GECCO
2006
Springer
13 years 11 months ago
2006
Springer
In this paper, a genetic algorithm (GA) is used to design faulttolerant analog controllers for a piezoelectric micro-robot. Firstorder and second-order functions are developed to ...
SLIP
2005
ACM
14 years 1 months ago
2005
ACM
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
GLVLSI
2010
IEEE
14 years 16 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...