281 search results - page 18 / 57 » On the Hardware Implementation Cost of Crypto-Processors Arc... |
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
ITC
2003
IEEE
14 years 28 days ago
2003
IEEE
Today’s low cost wireless phones have driven a need to be able to economically test high volumes of complex RF IC’s at a fraction of the cost of the IC. In June of 2001 the IB...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
DATE
2002
IEEE
14 years 19 days ago
2002
IEEE
The minimization of cost, power consumption and timeto-market of DSP applications requires the development of methodologies for the automatic implementation of floating-point alg...