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MICRO
1997
IEEE
110views Hardware» more  MICRO 1997»
13 years 12 months ago
The Design and Performance of a Conflict-Avoiding Cache
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
Nigel P. Topham, Antonio González, Jos&eacu...
PLSA
1994
13 years 11 months ago
Language and Architecture Paradigms as Object Classes
Computer language paradigms offer linguistic abstractions and proof theories for expressing program implementations. Similarly, system architectures offer the hardware abstractions...
Diomidis Spinellis, Sophia Drossopoulou, Susan Eis...
ISCAS
2008
IEEE
287views Hardware» more  ISCAS 2008»
14 years 2 months ago
A high speed word level finite field multiplier using reordered normal basis
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad...
TC
2011
13 years 2 months ago
An Architecture for Fault-Tolerant Computation with Stochastic Logic
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...
Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan...
CORR
2006
Springer
103views Education» more  CORR 2006»
13 years 7 months ago
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not always run on new hardware and operating systems, threatening the long-term usability of content archiv...
Bryan Ford