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ECBS
2006
IEEE
203views Hardware» more  ECBS 2006»
13 years 11 months ago
The Feature-Architecture Mapping (FArM) Method for Feature-Oriented Development of Software Product Lines
Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are sca...
Periklis Sochos, Matthias Riebisch, Ilka Philippow
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
14 years 1 days ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 1 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
ACSAC
2003
IEEE
14 years 1 months ago
MLS-PCA: A High Assurance Security Architecture for Future Avionics
1 DOD Joint Vision 2020 (JV2020) is the integrated multi-service planning document for conduct among coalition forces of future warfare. It requires the confluence of a number of k...
Clark Weissman
ASPLOS
2010
ACM
14 years 2 months ago
Flexible architectural support for fine-grain scheduling
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis