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ICCD
2007
IEEE
146views Hardware» more  ICCD 2007»
14 years 4 months ago
Exploring DRAM cache architectures for CMP server platforms
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald New...
EMSOFT
2010
Springer
13 years 5 months ago
Reducing stack with intra-task threshold priorities in real-time systems
In the design of hard real-time systems, the feasibility of the task set is one of the primary concerns. However, in embedded systems with scarce resources, optimizing resource us...
Gang Yao, Giorgio C. Buttazzo
SDM
2009
SIAM
173views Data Mining» more  SDM 2009»
14 years 4 months ago
Discretized Spatio-Temporal Scan Window.
The focus of this paper is the discovery of anomalous spatio-temporal windows. We propose a Discretized SpatioTemporal Scan Window approach to address the question of how we can t...
Aryya Gangopadhyay, Seyed H. Mohammadi, Vandana Pu...
JUCS
2006
112views more  JUCS 2006»
13 years 7 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
IPPS
2006
IEEE
14 years 1 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González