340 search results - page 29 / 68 » On the Interplay of Parallelization, Program Performance, an... |
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
This work presents the development of a coarse grain reconfigurable unit to be coupled to a native Java microcontroller, which is designed for an optimized execution of the embedd...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
HOTOS
1999
IEEE
14 years 24 days ago
1999
IEEE
Reducing the energy consumed in the use of computing devices is becoming a major design challenge. While the problem obviously must be addressed with improved low-level technology...
PLDI
2003
ACM
14 years 1 months ago
2003
ACM
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...