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» On the Limitations of Power Macromodeling Techniques
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TON
2008
125views more  TON 2008»
13 years 7 months ago
Two techniques for fast computation of constrained shortest paths
Abstract-- Computing constrained shortest paths is fundamental to some important network functions such as QoS routing, which is to find the cheapest path that satisfies certain co...
Shigang Chen, Meongchul Song, Sartaj Sahni
JSAC
2006
100views more  JSAC 2006»
13 years 7 months ago
Analysis and optimization of CDMA systems with chip-level interleavers
Abstract--In this paper, we present an unequal power allocation technique to increase the throughput of code-division multiple-access (CDMA) systems with chip-level interleavers. P...
Lihai Liu, Jun Tong, Li Ping
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda
ISVLSI
2002
IEEE
81views VLSI» more  ISVLSI 2002»
14 years 10 days ago
Impact of Technology Scaling in the Clock System Power
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
14 years 21 days ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar