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» On the Limitations of Power Macromodeling Techniques
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ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
14 years 1 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
14 years 4 months ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
VLSI
2010
Springer
13 years 5 months ago
Trends and techniques for energy efficient architectures
Abstract--Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more than any o...
Victor Jimenez, Roberto Gioiosa, Eren Kursun, Fran...
ISCA
2007
IEEE
168views Hardware» more  ISCA 2007»
14 years 1 months ago
Limiting the power consumption of main memory
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...
Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Me...
GI
2001
Springer
13 years 12 months ago
Improving Goodput by Relaying in Transmission-Power-Limited Wireless Systems
In wireless communication systems, the capacity of a cell (the amount of correctly delivered traffic in unit time) is a precious resource that can not be arbitrarily increased. T...
Seble Mengesha, Holger Karl, Adam Wolisz