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CASES
2007
ACM
13 years 12 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
CODES
2009
IEEE
14 years 2 months ago
FRA: a flash-aware redundancy array of flash storage devices
Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage med...
Yangsup Lee, Sanghyuk Jung, Yong Ho Song
CHES
2008
Springer
132views Cryptology» more  CHES 2008»
13 years 10 months ago
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
Bit-slicing is a non-conventional implementation technique for cryptographic software where an n-bit processor is considered as a collection of n 1-bit execution units operating in...
Philipp Grabher, Johann Großschädl, Dan...
IPPS
2007
IEEE
14 years 2 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
ITC
2003
IEEE
168views Hardware» more  ITC 2003»
14 years 1 months ago
Agent Based DBIST/DBISR And Its Web/Wireless Management
This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) an...
Liviu Miclea, Szilárd Enyedi, Gavril Todere...