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NOCS
2009
IEEE
14 years 2 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
AINA
2007
IEEE
14 years 2 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
CEC
2010
IEEE
13 years 8 months ago
Genetic programming for Expert Systems
— Genetic programming is the usage of the paradigm of survival of the fittest in scientific computing. It is applied to evolve solutions to problems where dependencies between ...
Konrad Sickel, Joachim Hornegger
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 7 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DATE
2003
IEEE
101views Hardware» more  DATE 2003»
14 years 1 months ago
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
In this paper, we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic rout...
Jingcao Hu, Radu Marculescu