Sciweavers

502 search results - page 76 / 101
» On the Practical Performance of Rateless Codes
Sort
View
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
TCOM
2008
115views more  TCOM 2008»
13 years 7 months ago
Differentiated rate scheduling for the down-link of cellular systems
We consider the problem of differentiated rate scheduling for the downlink (i.e., multi-antenna broadcast channel), in the sense that the rates required by different users must sat...
Amir F. Dana, Masoud Sharif, Ali Vakili, Babak Has...
UAIS
2008
104views more  UAIS 2008»
13 years 7 months ago
A knowledge-based sign synthesis architecture
This paper presents the modules that comprise a knowledge-based sign synthesis architecture for Greek sign language (GSL). Such systems combine natural language (NL) knowledge, mac...
Stavroula-Evita Fotinea, Eleni Efthimiou, George C...
BMCBI
2005
153views more  BMCBI 2005»
13 years 7 months ago
A comparative review of estimates of the proportion unchanged genes and the false discovery rate
Background: In the analysis of microarray data one generally produces a vector of p-values that for each gene give the likelihood of obtaining equally strong evidence of change by...
Per Broberg
SIGSOFT
2007
ACM
14 years 8 months ago
Measuring empirical computational complexity
The standard language for describing the asymptotic behavior of algorithms is theoretical computational complexity. We propose a method for describing the asymptotic behavior of p...
Simon Goldsmith, Alex Aiken, Daniel Shawcross Wilk...