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ICPP
2008
IEEE
14 years 1 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
13 years 5 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...
RTCSA
2007
IEEE
14 years 1 months ago
A Real-Time Database Testbed and Performance Evaluation
A lot of real-time database (RTDB) research has been done to process transactions in a timely fashion using fresh data reflecting the current real world status. However, most exi...
Kyoung-Don Kang, Phillip H. Sin, Jisu Oh
ICAC
2009
IEEE
14 years 2 months ago
Resilient workload manager: taming bursty workload of scaling internet applications
In data centers hosting scaling Internet applications, operators face the tradeoff dilemma between resource efficiency and Quality of Service (QoS), and the root cause lies in wo...
Hui Zhang 0002, Guofei Jiang, Kenji Yoshihira, Hai...
MICRO
2008
IEEE
148views Hardware» more  MICRO 2008»
14 years 1 months ago
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
—Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although sever...
Ramazan Bitirgen, Engin Ipek, José F. Mart&...