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ISMVL
2007
IEEE
245views Hardware» more  ISMVL 2007»
16 years 3 days ago
Fault Tolerant CMOS Logic Using Ternary Gates
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
Yngvar Berg, Renè Jensen, Johannes Goplen L...
ICA
2007
Springer
16 years 2 hour ago
A Robust Complex FastICA Algorithm Using the Huber M-Estimator Cost Function
In this paper, we propose to use the Huber M-estimator cost function as a contrast function within the complex FastICA algorithm of Bingham and Hyvarinen for the blind separation o...
Jih-Cheng Chao, Scott C. Douglas
SCAM
2005
IEEE
15 years 11 months ago
Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions
Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to...
Nerina Bermudo, Andreas Krall, R. Nigel Horspool
DATE
2000
IEEE
134views Hardware» more  DATE 2000»
15 years 10 months ago
An on Chip ADC Test Structure
In this paper, a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator ...
Yun-Che Wen, Kuen-Jong Lee
ESANN
2004
15 years 7 months ago
Learning by geometrical shape changes of dendritic spines
The role of dendritic spines in neuronal information processing is still not completely clear. However, it is known that spines can change shape rapidly during development and duri...
Andreas Herzog, Vadym Spravedlyvyy, Karsten Kube, ...