39 search results - page 4 / 8 » On the Relation between SAT and BDDs for Equivalence Checkin... |
ASPDAC
2007
ACM
13 years 12 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
Multiple clock domains are a challenge for hardware specification and verification. We present a method for specifying the relations between multiple clocks, and for modeling th...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
CSAC
2006
13 years 9 months ago
2006
Abstract. Web services constitute a dynamic field of research about technologies of the Internet. WS-BPEL 2.0, is in the way for becoming a standard for defining Web services orche...
LPAR
2010
Springer
13 years 5 months ago
2010
Springer
We investigate the complexity of preorder checking when the specification is a flat finite-state system whereas the implementation is either a non-flat finite-state system or a st...