We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
Abstract: Models of the dynamics of cellular interaction networks have become increasingly larger in recent years. Formal verification based on model checking provides a powerful t...
Pedro T. Monteiro, Delphine Ropers, Radu Mateescu,...
Embedded systems are pervasive and frequently used for critical systems with time-dependent functionality. Dwyer et al. have developed qualitative specification patterns to facili...
Verifying security properties of protocols requires developers to manually create protocol-specific intruder models, which could be tedious and error prone. We present Slede, a ve...
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...