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HPCA
2005
IEEE
14 years 3 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
AINA
2010
IEEE
14 years 3 months ago
Routing Loops in DAG-Based Low Power and Lossy Networks
Abstract—Directed Acyclic Graphs (DAGs), rooted at popular/default destinations, have emerged as a preferred mechanism to provide IPv6 routing functionality in large scale low po...
Weigao Xie, Mukul Goyal, Hossein Hosseini, Jerald ...
DAC
1999
ACM
14 years 2 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
DAC
1999
ACM
14 years 2 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
SCW
2012
IEEE
12 years 5 months ago
Linear cost share equilibria and the veto power of the grand coalition
We consider pure exchange economies with finitely many private goods involving the choice of a public project. We discuss core-equivalence results in the general framework of non...
Maria Gabriella Graziano, Maria Romaniello