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» On the energy-efficiency of speculative hardware
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DATE
2004
IEEE
144views Hardware» more  DATE 2004»
14 years 1 months ago
Cache-Aware Scratchpad Allocation Algorithm
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
Manish Verma, Lars Wehmeyer, Peter Marwedel
DSD
2004
IEEE
132views Hardware» more  DSD 2004»
14 years 1 months ago
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Filter cache(FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
14 years 2 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
ASPLOS
1992
ACM
14 years 2 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
DATE
1999
IEEE
82views Hardware» more  DATE 1999»
14 years 2 months ago
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation
Emerging design problems are prompting the use of code motion and speculation in high
Luiz C. V. dos Santos, Jochen A. G. Jess