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» On the energy-efficiency of speculative hardware
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ISCA
1999
IEEE
104views Hardware» more  ISCA 1999»
14 years 1 months ago
Is SC + ILP=RC?
Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high perform...
Chris Gniady, Babak Falsafi, T. N. Vijaykumar
HPCA
2002
IEEE
14 years 9 months ago
Improving Value Communication for Thread-Level Speculation
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
14 years 1 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
ISLPED
2000
ACM
101views Hardware» more  ISLPED 2000»
14 years 1 months ago
Design issues for dynamic voltage scaling
Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the proc...
Thomas D. Burd, Robert W. Brodersen
DATE
2009
IEEE
64views Hardware» more  DATE 2009»
14 years 25 days ago
Speculative reduction-based scalable redundancy identification
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inhere...
Hari Mony, Jason Baumgartner, Alan Mishchenko, Rob...