415 search results - page 66 / 83 » On the energy-efficiency of speculative hardware |
ISCA
2010
IEEE
14 years 22 days ago
2010
IEEE
Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the se...
ISSS
2002
IEEE
14 years 17 days ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...