415 search results - page 68 / 83 » On the energy-efficiency of speculative hardware |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
ISSS
2002
IEEE
14 years 16 days ago
2002
IEEE
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
MICRO
2002
IEEE
14 years 16 days ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...