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» On the energy-efficiency of speculative hardware
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MICRO
1999
IEEE
104views Hardware» more  MICRO 1999»
13 years 12 months ago
Control Independence in Trace Processors
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
Eric Rotenberg, James E. Smith
ISCA
1998
IEEE
102views Hardware» more  ISCA 1998»
13 years 12 months ago
Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predic...
Toni Juan, Sanji Sanjeevan, Juan J. Navarro
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
13 years 12 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 12 months ago
Better Global Scheduling Using Path Profiles
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
Cliff Young, Michael D. Smith
ISCA
1993
IEEE
113views Hardware» more  ISCA 1993»
13 years 11 months ago
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History
Recent attention to speculative execution as a mechanism for increasing performance of single instruction streams has demanded substantially better branch prediction than what has...
Tse-Yu Yeh, Yale N. Patt