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VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 9 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
CVPR
2010
IEEE
14 years 5 months ago
Nonparametric Higher-Order Learning for Interactive Segmentation
In this paper, we deal with a generative model for multi-label, interactive segmentation. To estimate the pixel likelihoods for each label, we propose a new higher-order formulatio...
Tae Hoon Kim (Seoul National University), Kyoung M...
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
14 years 3 months ago
Energy efficient multiprocessor task scheduling under input-dependent variation
— In this paper, we propose a novel, energy aware scheduling algorithm for applications running on DVS-enabled multiprocessor systems, which exploits variation in execution times...
Jason Cong, Karthik Gururaj
ISCC
2009
IEEE
210views Communications» more  ISCC 2009»
14 years 3 months ago
Towards a Java bytecodes compiler for Nios II soft-core processor
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
Willian dos Santos Lima, Renata Spolon Lobato, Ale...
WABI
2009
Springer
181views Bioinformatics» more  WABI 2009»
14 years 3 months ago
Decoding Synteny Blocks and Large-Scale Duplications in Mammalian and Plant Genomes
Abstract. The existing synteny block reconstruction algorithms use anchors (e.g., orthologous genes) shared over all genomes to construct the synteny blocks for multiple genomes. T...
Qian Peng, Max A. Alekseyev, Glenn Tesler, Pavel A...