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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 15 days ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
14 years 7 days ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
CCO
2001
Springer
168views Combinatorics» more  CCO 2001»
13 years 12 months ago
Mathematical Programming Models and Formulations for Deterministic Production Planning Problems
Abstract. We study in this lecture the literature on mixed integer programming models and formulations for a specific problem class, namely deterministic production planning probl...
Yves Pochet
ICC
2000
IEEE
137views Communications» more  ICC 2000»
13 years 11 months ago
Internet QoS Routing with IP Telephony and TCP Traffic
— In this paper, we propose the use of QoS routing to enhance the support of IP Telephony. Our proposed scheme is based on QoS intradomain OSPF routing, an extension of the conve...
Alex Dubrovsky, Mario Gerla, Scott Seongwook Lee, ...
INFOCOM
1998
IEEE
13 years 11 months ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang