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» On the power of coercion abstraction
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ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 1 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ICC
2009
IEEE
152views Communications» more  ICC 2009»
14 years 2 months ago
Centralized and Distributed Power Allocation in Multi-User Wireless Relay Networks
Abstract—Optimal power allocation for multi-user amplifyand-forward wireless relay networks in which multiple sourcedestination pairs are assisted by a set of relays is investiga...
Khoa T. Phan, Long Bao Le, Sergiy A. Vorobyov, Tho...
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 4 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
13 years 12 months ago
A Discrete-Time Battery Model for High-Level Power Estimation
In this paper, we introduce a discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-t...
Luca Benini, Giuliano Castelli, Alberto Macii, Enr...
VLSI
2012
Springer
12 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel