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» On the rules of intermediate logics
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ISQED
2005
IEEE
133views Hardware» more  ISQED 2005»
14 years 1 months ago
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...
APLAS
2004
ACM
14 years 1 months ago
Translation of Tree-Processing Programs into Stream-Processing Programs Based on Ordered Linear Type
There are two ways to write a program for manipulating tree-structured data such as XML documents: One is to write a tree-processing program focusing on the logical structure of t...
Koichi Kodama, Kohei Suenaga, Naoki Kobayashi
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
14 years 1 months ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
14 years 23 days ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...