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» On two-step routing for FPGAS
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ICCD
1994
IEEE
157views Hardware» more  ICCD 1994»
13 years 10 months ago
Mesh Routing Topologies for Multi-FPGA Systems
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
Scott Hauck, Gaetano Borriello, Carl Ebeling
FPGA
2000
ACM
141views FPGA» more  FPGA 2000»
13 years 10 months ago
Tolerating operational faults in cluster-based FPGAs
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
Vijay Lakamraju, Russell Tessier
EH
1999
IEEE
161views Hardware» more  EH 1999»
13 years 11 months ago
Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
John F. McDonald, Bryan S. Goda
FPL
2008
Springer
107views Hardware» more  FPL 2008»
13 years 8 months ago
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
ITC
1998
IEEE
104views Hardware» more  ITC 1998»
13 years 11 months ago
Built-in self-test of FPGA interconnect
: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affect...
Charles E. Stroud, Sajitha Wijesuriya, Carter Hami...