170 search results - page 22 / 34 » On two-step routing for FPGAS |
FPGA
2001
ACM
13 years 11 months ago
2001
ACM
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
CSREAESA
2010
13 years 4 months ago
2010
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
FCCM
2009
IEEE
13 years 10 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
ICCAD
2007
IEEE
14 years 3 months ago
2007
IEEE
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
FPGA
2001
ACM
13 years 11 months ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...