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    » On two-step routing for FPGAS
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    ICDE
    2009
    IEEE
    140views Database» more  ICDE 2009»
    Routing Questions to the Right Users in Online Communities
    13 years 4 months ago
    Routing Questions to the Right Users in Online Communities
    Download  www.cs.aau.dk
    Online forums contain huge amounts of valuable user-generated content. In current forum systems, users have to passively wait for other users to visit the forum systems and read/an...
    Yanhong Zhou, Gao Cong, Bin Cui, Christian S. Jens...
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    FPGA
    1999
    ACM
    115views FPGA» more  FPGA 1999»
    Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
    13 years 11 months ago
    Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
    Download  www.eecg.toronto.edu
    In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
    Alexander Marquardt, Vaughn Betz, Jonathan Rose
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    ASPDAC
    2005
    ACM
    89views Hardware» more  ASPDAC 2005»
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
    13 years 8 months ago
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
    Download  www.ee.ucla.edu
    Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
    Yan Lin, Fei Li, Lei He
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    FPGA
    2004
    ACM
    145views FPGA» more  FPGA 2004»
    Exploration of pipelined FPGA interconnect structures
    14 years 4 days ago
    Exploration of pipelined FPGA interconnect structures
    Download  www.ece.wisc.edu
    In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
    Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
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    FCCM
    2005
    IEEE
    139views VLSI» more  FCCM 2005»
    A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
    14 years 11 days ago
    A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
    Download  www.cs.ucr.edu
    Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
    Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
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