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» On two-step routing for FPGAS
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DAC
2003
ACM
13 years 12 months ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
ISVLSI
2005
IEEE
80views VLSI» more  ISVLSI 2005»
14 years 8 days ago
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
Renqiu Huang, Ranga Vemuri
FPL
2005
Springer
114views Hardware» more  FPL 2005»
14 years 7 days ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
FPGA
1998
ACM
176views FPGA» more  FPGA 1998»
13 years 11 months ago
A Fast Routability-Driven Router for FPGAs
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute powe...
Jordan S. Swartz, Vaughn Betz, Jonathan Rose
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
14 years 4 days ago
Interconnect design methods for memory design
- This paper presents a solution to the problem of designing interconnects for memory devices. More precisely, it solves the automatic routing problem of memory peripheral circuits...
Chanseok Hwang, Massoud Pedram