A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...