9 search results - page 2 / 2 » On-chip interconnect modeling by wire duplication |
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L 1 matrix, where L is the ...
SLIP
2009
ACM
14 years 3 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
ASPDAC
2001
ACM
14 years 6 days ago
2001
ACM
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...