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CODES
2006
IEEE
14 years 1 months ago
Thermal-aware high-level synthesis based on network flow method
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reli...
Pilok Lim, Taewhan Kim
INFOCOM
2006
IEEE
14 years 1 months ago
Backbone Topology Synthesis for Multi-Radio Meshed Wireless LANs
—Wireless local area network (WLAN) systems are widely implemented today to provide hot spot coverage. Operated typically in an infrastructure mode, each WLAN is managed by an ac...
Laura Huei-jiun Ju, Izhak Rubin
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 2 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
13 years 11 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
HICSS
2009
IEEE
129views Biometrics» more  HICSS 2009»
14 years 2 months ago
Identifying Organizational Knowledge Paths through Social Network Lens: Synthesis of Multi-Industry Case Studies
Unlike the common belief that knowledge flows mainly along the formal organizational hierarchy, recent research has pointed out an informal social network among organizational mem...
Young-Gul Kim, Sung-Byung Yang, Yong-Sauk Hau, Jeo...