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ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
14 years 10 days ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
MSE
1999
IEEE
118views Hardware» more  MSE 1999»
13 years 12 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
DAC
1995
ACM
13 years 11 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
DAC
2005
ACM
13 years 9 months ago
Minimizing peak current via opposite-phase clock tree
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
AIPS
1998
13 years 9 months ago
Encoding HTN Planning in Propositional Logic
Casting planning problems as propositional satis ability problems has recently been shown to be an effective way of scaling up plan synthesis. Until now, the bene ts of this appro...
Amol Dattatraya Mali, Subbarao Kambhampati