Sciweavers

510 search results - page 90 / 102
» Online Performance Observation of Large-Scale Parallel Appli...
Sort
View
ICDCS
2010
IEEE
14 years 14 days ago
LT Network Codes
This paper proposes LTNC, a new recoding algorithm to build low complexity network codes. At the core of LTNC is a decentralized version of LT codes that allows the use of fast be...
Mary-Luc Champel, Kévin Huguenin, Anne-Mari...
HPCA
2003
IEEE
14 years 9 months ago
Memory System Behavior of Java-Based Middleware
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...
Martin Karlsson, Kevin E. Moore, Erik Hagersten, D...
HPCA
2011
IEEE
13 years 9 days ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 29 days ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
HPCA
2005
IEEE
14 years 9 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob