7 search results - page 1 / 2 » Online cache state dumping for processor debug |
DAC
2009
ACM
15 years 5 days ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
SIGOPS
2010
13 years 5 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
IEEEPACT
2005
IEEE
14 years 4 months ago
2005
IEEE
We propose a checkpoint store compression method for coarse-grain giga-scale checkpoint/restore. This mechanism can be useful for debugging, post-mortem analysis and error recover...
ISCA
2010
IEEE
14 years 4 months ago
2010
IEEE
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...