In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
In many emerging applications, data streams are monitored in a network environment. Due to limited communication bandwidth and other resource constraints, a critical and practical...
In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide theoretical analysis for the p...
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Suda...
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...